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Flash Memory Of Upgraded Versions Available Online

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S25FL128LAGNFI010, Cypress Semiconductor

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S25FL064LABMFA001, Cypress Semiconductor

The FL-L family connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output(Single I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit wide Quad I/O (QIO) and Quad Peripheral Interface (QPI) commands. In addition, there are Double Data Rate (DDR) read commands for QIO and QPI that transfer address and read data on both edges of the clock.The architecture features a Page Programming Buffer that allows up to 256 bytes to be programmed in one operation and providesindividual 4 KB sector, 32 KB half block sector, 64 KB block sector, or entire chip erase.By using FL-L family devices at the higher clock rates supported, with Quad commands, the instruction read transfer rate can match or exceed traditional parallel interface, asynchronous, NOR Flash memories, while reducing signal count dramatically.The FL-L family products offer high densities coupled with the flexibility and fast performance required by a variety of mobile or embedded applications. Provides an ideal storage solution for systems with limited space, signal connections and power. These memories offer flexibility and performance well beyond ordinary serial flash devices. They are ideal for code shadowing to RAM,executing code directly (XIP) and storing re-programmable data.

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S25FL256SAGMFIG01, Cypress Semiconductor

Serial-SPI NOR Flash Memory, Cypress Semiconductor High performance Low pin-count Quad SPI (Serial Peripheral Interface) Flash Memory FLASH Memory IC is a non-volatile RAM that has to be written/erased in blocks. It does have a limited life in terms of number of write cycles and tends to be used for program storage that is infrequently changed.

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S70FL01GSAGMFI011, Cypress Semiconductor

Serial-SPI NOR Flash Memory, Cypress Semiconductor High performance Low pin-count Quad SPI (Serial Peripheral Interface) Flash Memory FLASH Memory IC is a non-volatile RAM that has to be written/erased in blocks. It does have a limited life in terms of number of write cycles and tends to be used for program storage that is infrequently changed.

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S29GL128P11FFI020, Cypress Semiconductor

The Cypress S29GL01G/512/256/128P are Mirrorbit® Flash products fabricated on 90 nm process technology. These devices offer a fast page access time of 25 ns with a corresponding random access time as fast as 90 ns. They feature a Write Buffer that allows a maximum of 32 words/64 bytes to be programmed in one operation, resulting in faster effective programming time than standard programming algorithms. This makes these devices ideal for todays embedded applications that require higher density, better performance and lower power consumption.

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S29AL008J70TFI013, Cypress Semiconductor

The S29AL008J is a 8 Mbit, 3.0 Volt-only Flash memory organized as 1,048,576 bytes or 524,288 words. The device is offered in 48-ball Fine-pitch BGA (0.8 mm pitch) and 48pin TSOP packages. The word-wide data (x16) appears on DQ15–DQ0, the byte-wide (x8) data appears on DQ7–DQ0. This device is designed to be programmed in-system with the standard system 3.0 volt VCC supply. A 12.0 V VPP or 5.0 VCC are not required for write or erase operations. The device can also be programmed in standard EPROM programmers.The device offers access times of up to 55 ns allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four.Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. Duringerase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7(Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.

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S29GL512T11FHIV20, Cypress Semiconductor

63 nm MirrorBit Eclipse TechnologySingle supply (VCC) for read / program / erase (2.7 V to 3.6 V)Versatile I/O featureWide I/O voltage range (VIO): 1.65 V to VCCx8/x16 data busAsynchronous 32-byte Page read512-byte Programming BufferProgramming in 12 bytesSingle word and multiple program on same word optionsAutomatic Error Checking and Correction (ECC) internal hardware ECC with single bit error correctionSector EraseUniform 128-KB sectorsSuspend and Resume commands for Program and Erase operationsStatus Register, Data Polling and Ready/Busy pin methods to determine device status Advanced Sector Protection (ASP)Volatile and non-volatile protection methods for each sectorSeparate 2048-byte One-Time Program (OTP) arrayFour lockable regions (SSR0 - SSR3)SSR0 is Factory LockedSSR3 is Password Read ProtectCommon Flash Interface (CFI) parameter tableTemperature Range / Grade:Industrial (-40 °C to +85 °C)Industrial Plus (-40 °C to +105 °C)Extended (-40 °C to +125 °C)100,000 Program / Erase Cycles20-year data retention፤

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SST39VF3201-70-4C-EKE, Microchip

SST39VF3201/3202 Parallel SuperFlash® Memory Flash Memory, Microchip

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S25FS512SAGMFI011, Cypress Semiconductor

The S25FS512S connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output(Single I/O or SIO) is supported as well as optional twobit (Dual I/O or DIO) and fourbit wide Quad I/O (QIO) or Quad PeripheralInterface (QPI) serial commands. This multiple-width interface is called SPI Multi-I/O or MIO. In addition, there are Double Data Rate(DDR) read commands for QIO and QPI that transfer address and read data on both edges of the clock.The FS-S Eclipse architecture features a Page Programming Buffer that allows up to 512 bytes to be programmed in one operation,resulting in faster effective programming and erase than prior generation SPI program or erase algorithms. Executing code directly from flash memory is often called Execute-In-Place or XIP. By using S25FS512S devices at the higher clockrates supported, with Quad or DDR-Quad commands, the instruction read transfer rate can match or exceed traditional parallel interface, asynchronous, NOR flash memories, while reducing signal count dramatically.The S25FS512S products offer high densities coupled with the flexibility and fast performance required by a variety of mobile or embedded applications. They are an excellent solution for systems with limited space, signal connections and power. They are ideal forcode shadowing to RAM, executing code directly (XIP) and storing reprogrammable data.

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New items

S25FL064LABNFI010, Cypress Semiconductor

The FL-L family connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output(Single I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit wide Quad I/O (QIO) and Quad Peripheral Interface (QPI) commands. In addition, there are Double Data Rate (DDR) read commands for QIO and QPI that transfer address and read data on both edges of the clock.The architecture features a Page Programming Buffer that allows up to 256 bytes to be programmed in one operation and providesindividual 4 KB sector, 32 KB half block sector, 64 KB block sector, or entire chip erase.By using FL-L family devices at the higher clock rates supported, with Quad commands, the instruction read transfer rate can match or exceed traditional parallel interface, asynchronous, NOR Flash memories, while reducing signal count dramatically.The FL-L family products offer high densities coupled with the flexibility and fast performance required by a variety of mobile or embedded applications. Provides an ideal storage solution for systems with limited space, signal connections and power. These memories offer flexibility and performance well beyond ordinary serial flash devices. They are ideal for code shadowing to RAM,executing code directly (XIP) and storing re-programmable data.

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SST25VF016B-50-4I-S2AF-T, Microchip

SST's 25 series Serial Flash family features a four-wire, SPI-compatible interface that allows for a low pin-count package which occupies less board space and ultimately lowers total system costs. The SST25VF016B devices are enhanced with improved operating frequency which lowers power consumption. SST25VF016B SPI serial flash memories are manufactured with SST's proprietary, high-performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. Single Voltage Read and Write Operations Serial Interface Architecture High Speed Clock Frequency Hold Pin - Suspend a serial sequence without deselecting the device Write Protection - Enables/Disables the Lock-Down function of the status register Software Write Protection - Write protection through Block-Protection bits in status register Temperature Range -40°C to +85°C

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S25HS512TDPMHI010, Cypress Semiconductor

Cypress NOR Flash Memory is a non-volatile storage solution that integrates safety features for automotive and industrial systems. Applications include automotive instrument clusters, advanced driver assistance systems (ADAS), and networking communications. EnduraFlex™ Architecture: Partition memory to provide up to 25-years data retention and 1+ million program/erase cycles endurance, JEDEC xSPI compatible, Data Integrity Check and Interface CRC Certificates: ISO 26262 ASIL B Compliant, ISO 26262 ASIL-D ready. FMEDA and safety manual Single error correction and double error detection (SECDED) SafeBoot

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