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Clock Buffers | Clock Timing

New items

CY2305SXI-1T, Infineon

The Infineon Zero delay buffer designed to distribute high speed clocks and is available in a 8 pin SOIC package. It accepts one reference input and drives out five low skew clocks. All parts have on chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on chip and is obtained from the CLKOUT pad. Multiple low skew outputs 60 ps typical cycle to cycle jitter Zero input output propagation delay Compatible with Pentium based systems

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New items

9DB803DFILF, Renesas Electronics

The Renesas Electronics eight output differential buffer for PCIE gen1 and gen2 is compatible with intel differential buffer specification. This buffer provides 8 PCI-Express Gen2 clocks. It is driven by a differential output pair of main clock generator. Supports zero delay buffer mode and fan out mode Bandwidth programming available

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9DML4493ANLGI, Renesas Electronics

The Renesas Electronics 4-input, 4-output clock multiplexer. It can also operate as a dual 2-input, 2-output clock multiplexer. It has very low additive phase jitter and is suitable for all PCIe data rates. The device supports todays complex system power sequencing requirements with Power Down Tolerant and Flexible Power Sequencing features. Supports common Clocked (CC) and IR (SRIS, SRNS) timing architectures Glitch-free output enable pins for each output Spread-spectrum tolerant

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New items

5PB1204CMGK, Renesas Electronics

The Renesas Electronics Mix signal is a high-performance TCXO / LVCMOS clock fan-out buffer with individual OE pin for each output. The CLKIN pin can accept either a square wave or clipped sine wave as input. The mix signal has industry-leading low jitter and extremely low current consumption, making it ideal for smart mobile devices. Extremely low operating and standby current consumption Low RMS additive phase jitter 1.8 V power supply voltage Four outputs with individual output enable pin

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New items

CY2305SXI-1, Cypress Semiconductor

10 MHz to 100/133 MHz operating range, compatible with CPU and PCI bus frequenciesZero input-output propagation delay60-ps typical cycle-to-cycle jitter (high drive)Multiple low skew outputs85 ps typical output-to-output skew One input drives five outputs (CY2305)One input drives nine outputs, grouped as 4 + 4 + 1 (CY2309)Compatible with Pentium-based systemsTest Mode to bypass phase-locked loop (PLL) (CY2309)Packages: 8-pin, 150-mil SOIC package (CY2305)16-pin 150-mil SOIC or 4.4-mm TSSOP (CY2309)3.3 V operationCommercial and industrial temperature ranges

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New items

9DB433AGLFT, Renesas Electronics

The Renesas Electronics 9DB433 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB433 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. Output cycle-cycle jitter <50ps Output to Output skew <50ps Phase jitter: PCIe Gen3 <1.0ps rms

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New items

2305NZ-1HDCGI, Renesas Electronics

The Renesas Electronics IDT2305NZ is a low-cost buffer designed to distribute high-speed clocks in mobile PC systems and desktop PC systems. The IDT2305NZ operates at 3.3V with five outputs that can run up to 133.33MHz The IDT2305NZ is an 8-pin version of the IDT2309NZ. It is designed for low EMI and power optimization and consumes less than 32mA at 66.6MHz, making it ideal for the low power requirements of mobile systems. One input to five output buffer/driver Low power consumption for mobile applications: less than 32mA at 66.6MHz with unloaded outputs 8.7ns max input-output delay Buffers all frequencies from DC to 133.33MHz Output-output skew < 250ps 3.3V operation High drive capability

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New items

551MLF, Renesas Electronics

The Renesas Electronics 551 is a low cost, high-speed single input to four output clock buffer. Part of IDT's ClockBlocksTM family, this is our lowest cost, small clock buffer. See the 552-02B for monolithic dual version of the 551 in a 20 pin QSOP. IDT makes many non-PLL and PLL based low skew output devices as well as Zero Delay Buffers to synchronize clocks. Contact IDT for all of your clocking needs. Input/Output clock frequency up to 160 MHz Non-inverting output clock Ideal for networking clocks Operating Voltages of 3.3 and 5.0 V Output Enable mode tri-states outputs Advanced, low power CMOS process Commercial and industrial temperature versions

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New items

551SDCGI8, Renesas Electronics

The Renesas Electronics 551S series is a low cost, high-speed single input to four output clock buffer with best in class additive phase jitter of sub 50 fsec. The Renesas makes many non-PLL and PLL based low skew output devices as well as zero delay buffers to synchronize clocks. Low additive phase jitter RMS of 50fs and extremely low skew outputs (50ps) Low cost clock buffer and it has an input/output clock frequency up to 200MHz Packaged in 8-SOIC, 8-TSSOP and 8-DFN

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New items

9DB803DFLFT, Renesas Electronics

The Renesas Electronics ICS9DB803D is compatible with the Intel DB800v2 Differential Buffer Specification. This buffer provides 8 PCI-Express Gen2 clocks. The ICS9DB803D is driven by a differential output pair from a CK410B+, CK505 or CK509B main clock generator. 8 to 0.7V current-mode differential output pairs Supports zero delay buffer mode and fan-out mode

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New items

9ZXL0652EKILF, Renesas Electronics

The Renesas Electronics zero-delay/fan-out buffers with SMBus write protect is 2nd-generation enhanced performance buffer for PCIe and CPU applications. The device have hardware SMBUS write protection to prevent accidental writes. 6–12 Low-power HCSL (LP-HCSL) outputs Integrated terminations eliminate up to 4 resistors per output pair 85Ω output impedance 100MHz ZDB mode Spread spectrum compatible

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New items

CY2304SXI-2, Infineon

The CY2304 is a 3.3 V zero delay buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high performance applications. The part has an on-chip phase-locked loop (PLL) that locks to an input clock presented on the REF pin. The PLL feedback is required to be driven into the FBK pin, and can be obtained from one of the outputs. The input-to-output skew is guaranteed to be less than 250 ps, and output-to-output skew is guaranteed to be less than 200 ps. The CY2304 has two banks of two outputs each. The CY2304 PLL enters a power down state when there are no rising edges on the REF input. In this mode, all outputs are three-stated and the PLL is turned off, resulting in less than 25 μA of current draw. Multiple CY2304 devices can accept the same input clock and distribute it in a system. In this case, the skew between the outputs of two devices is guaranteed to be less than 500 ps. The CY2304 is available in two different configurations.

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