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Clock Buffers | Clock Timing

New items

CY23EP05SXC-1, Cypress Semiconductor

The CY23EP05 is a 2.5 V or 3.3 V zero delay buffer designed to distribute low-jitter high-speed clocks and is available in a 8-pin SOIC package. It accepts one reference input, and drives out five low-skew clocks. The -1H version operates up to 220 (200) MHz frequencies at 3.3 V (2.5 V), and has a higher drive strength than the -1 devices. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The CY23EP05 PLL enters a power-down mode when there are no rising edges on the REF input (

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CY2304SXI-2, Infineon

The CY2304 is a 3.3 V zero delay buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom, and other high performance applications. The part has an on-chip phase-locked loop (PLL) that locks to an input clock presented on the REF pin. The PLL feedback is required to be driven into the FBK pin, and can be obtained from one of the outputs. The input-to-output skew is guaranteed to be less than 250 ps, and output-to-output skew is guaranteed to be less than 200 ps. The CY2304 has two banks of two outputs each. The CY2304 PLL enters a power down state when there are no rising edges on the REF input. In this mode, all outputs are three-stated and the PLL is turned off, resulting in less than 25 μA of current draw. Multiple CY2304 devices can accept the same input clock and distribute it in a system. In this case, the skew between the outputs of two devices is guaranteed to be less than 500 ps. The CY2304 is available in two different configurations.

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CY2308SXI-1, Infineon

The CY2308 is a 3.3 V Zero Delay Buffer designed to distribute high speed clocks in PC, workstation, datacom, telecom, and other high performance applications. The part has an on-chip PLL that locks to an input clock presented on the REF pin. The PLL feedback is driven from external FBK pin, so user has flexibility to choose any one of the outputs as feedback input and connect it to FBK pin. The input-to-output skew is less than 250 ps and output-to-output skew is less than 200 ps. The CY2308 has two banks of four outputs each that is controlled by the select inputs as shown in the table Select Input Decoding on page 3. If all output clocks are not required, Bank B is three-stated. The input clock is directly applied to the output for chip and system testing purposes by the select inputs. The CY2308 PLL enters a power down state when there are no rising edges on the REF input. In this mode, all outputs are three-stated and the PLL is turned off resulting in less than 25 μA of current draw.

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CY23EP05SXC-1H, Infineon

The CY23EP05 is a 2.5 V or 3.3 V zero delay buffer designed to distribute low-jitter high-speed clocks and is available in a 8-pin SOIC package. It accepts one reference input, and drives out five low-skew clocks. The -1H version operates up to 220 (200) MHz frequencies at 3.3 V (2.5 V), and has a higher drive strength than the -1 devices. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. The CY23EP05 PLL enters a power-down mode when there are no rising edges on the REF input (< ∼2 MHz). In this state, the outputs are three-stated and the PLL is turned off, resulting in less than 25 μA of current draw. The CY23EP05 is available in different configurations. The CY23EP05-1 is the base part. The CY23EP05-1H is the high-drive version of the -1, and its rise and fall times are much faster than the -1. These parts are not intended for 5 V input-tolerant applications.

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9FGV0641AKILF, Renesas Electronics

The Renesas Electronics clock generator is a member of IDT's SOC-Friendly 1.8V very low-power PCIe clock family. The device has integrated 100ohm output terminations providing direction connection to 100ohm transmission lines. The device also has 6 output enables for clock management and supports 2 different spread spectrum levels in addition to spread off. LP-HCSL outputs with integrated terminations saves 24 resistors compared to standard PCIe devices 54mW typical power consumption which reduces thermal concerns Outputs can optionally be supplied from any voltage between 1.05V and 1.8V for maximum power savings Programmable slew rate for each output that allows tuning for various line lengths Programmable output amplitude allows tuning for various application environments DIF outputs blocked until PLL is locked for clean system start-up External 25MHz crystal which supports tight ppm with 0 ppm synthesis error 3.3V tolerant SMBus interface works with legacy controllers Selectable SMBus addresses as multiple devices can easily share an SMBus segment Space saving 5 x 5 mm 40-VFQFPN for minimal board space

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853S014AGILF, Renesas Electronics

The Renesas Electronics fan out buffer is of low skew, high performance 1 to 5, 2.5V/3.3V Differential to LVPECL/ECL. It has two selectable clock inputs. Guaranteed output and part to part skew characteristics makes it ideal for those applications demanding well defined performance and repeatability. It provides five differential LVPECL/ECL outputs It has two selectable differential LVPECL clock inputs Maximum output frequency is 2GHz Maximum output skew is 55ps Maximum part to part skew is 100ps Maximum propagation delay is 500ps Ambient operating temperature is -40°C to 85°C Consists of Lead-free packaging

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9DBL0452BKILFT, Renesas Electronics

The Renesas Electronics buffers are low power, high performance members of Renesas' full featured PCIe family. The buffers support PCIe Gen1 through Gen5. Spread spectrum compatible Dedicated output enable pin for each output One MHz to two hundred MHz operation in fan out mode Three selectable smbus addresses

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9DBL0442BKILF, Renesas Electronics

The Renesas Electronics buffers are low power, high performance members of Renesas full featured PCIe family. The buffers support PCIe Gen1 through Gen5. Spread spectrum compatible Dedicated output enable pin for each output One MHz to two hundred MHz operation in fan out mode Three selectable smbus addresses

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9DB403DFLF, Renesas Electronics

The Renesas Electronics 4-output differential buffer for PCIe Gen2 with the intel DB400v2 specification. It is driven by a differential output pair from a CK410B+, CK505 or CK509B main clock generator. Spread spectrum modulation tolerant, 0 to -0.5 % down spread and +/- 0.25 % center spread Supports undriven differential outputs in PD and SRC_STOP modes for power management

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9DB433AGLFT, Renesas Electronics

The Renesas Electronics 9DB433 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB433 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. Output cycle-cycle jitter <50ps Output to Output skew <50ps Phase jitter: PCIe Gen3 <1.0ps rms

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9DBV0841AKLF, Renesas Electronics

The Renesas Electronics PCIE ZDB/FO-BUFFER is a 1.8V member of Renesas full featured PCIe family. It has integrated output terminations providing Zo = 100Ω for direct connection for 100Ω transmission lines. The device has 8 output enables for clock management and 3 selectable SMBus addresses. LP-HCSL outputs save 32 resistors minimal board space and BOM cost 62mW typical power consumption in PLL mode eliminates thermal concerns Spread spectrum compatible allows use of SS for EMI reduction OE pins support DIF power management HCSL compatible differential input can be driven by common clock sources Programmable slew rate for each output allows tuning for various line lengths Programmable output amplitude allows tuning for various application environments

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552G-02ILN, Renesas Electronics

The Renesas Electronics 552-02 is a low skew, single-input to eight output clock buffer. The device offers a dual input with pin select for switching between two clock sources. It is part of IDT's ClockBlocksTM family. See the 553 for a 1 to 4 low skew buffer. For more than 8 outputs see the MK74CBxxx BuffaloTM series of clock drivers. IDT makes many non-PLL and PLL based low skew output devices as well as Zero Delay Buffers to synchronize clocks. Contact us for all of your clocking needs. Low power CMOS technology Operating Voltages of 2.5 V to 5 V Output Enable pin tri-states outputs 5 V tolerant input clocks Input/Output clock frequency up to 200 MHz Input clock multiplexer simplifies clock selection Industrial temperature

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