Toshiba TC4013BF(F) Dual D Type Flip Flop IC, 3 → 18 V, 14-Pin SOP
Product Information
Polarity:
Inverting, Non-Inverting
Dimensions:
10.3 x 5.3 x 1.5mm
Logic Family:
4000
Width:
5.3mm
Input Type:
Single Ended
Maximum Propagation Delay Time @ Maximum CL:
300 ns @ 5 V
Minimum Operating Supply Voltage:
3 V
Package Type:
SOP
Number of Elements per Chip:
2
Maximum Operating Temperature:
+85 °C
Set/Reset:
Yes
Output Signal Type:
Differential
Length:
10.3mm
Pin Count:
14
Maximum Operating Supply Voltage:
18 V
Mounting Type:
Surface Mount
Logic Function:
D Type
Height:
1.5mm
Minimum Operating Temperature:
-40 °C
Triggering Type:
Positive Edge
Propagation Delay Test Condition:
50pF
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FAQs
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You can order Toshiba brand products with TC4013BF(F) directly through our website or call us at +44 (0) 3303 800 157 or email our support team at sales@enrgtech.co.uk.
Yes. Our products in Flip Flop ICs category are shipped in lowest possible time.
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Yes. We ship TC4013BF(F) Internationally to many countries around the world.
This is Dual D Type Flip Flop IC 3 → 18 V 14-Pin SOP manufactured by Toshiba. The manufacturer part number is TC4013BF(F). While providing inverting, non-inverting polarity. The given dimensions of the product include 10.3 x 5.3 x 1.5mm. The logic family is 4000. Furthermore, the product is 5.3mm wide. It carries single ended input type. It provides up to 300 ns @ 5 v maximum propagation delay time. While its minimum operating supply voltage is 3 v. The package is a sort of sop. It consists of 2 elements per chip. It has a maximum operating temperature of +85 °c. It has a set/reset or yes feature . The output signal is a kind of differential. Its accurate length is 10.3mm. It contains 14 pins. It has 18 v maximum operating supply voltage. The product is available in surface mount configuration. The primary function of logic includes d type. In addition, the height is 1.5mm. Whereas, the minimum operating temperature of the product is -40 °c. It is tailored with a positive edge type triggering . Features 50pf of propagation delay test condition.
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