This is PLL Clock Buffer 100 → 100 MHz 28-Pin TSSOP manufactured by IDT. The manufacturer part number is ICS9DB106BGILF. The given dimensions of the product include 6.6 x 4.5 x 1.05mm. The product is available in surface mount configuration. Additionally, it has a maximum 100mhz output frequency . It has a minimum 100mhz output frequency . Moreover, it has a maximum 150 ma supply current . In addition, the height is 1.05mm. Furthermore, the product is 4.5mm wide. Its accurate length is 6.4mm. The product has a maximum 105mhz input frequency . The package is a sort of tssop. It consists of 1 elements per chip. Whereas, the minimum operating temperature of the product is -40 °c. It has 4.6 v maximum operating supply voltage. It has a maximum operating temperature of +85 °c. It contains 28 pins.
Zero delay PLL Clock buffer TSSOP28(Technical Reference)
ESD Control Selection Guide V1(Technical Reference)
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You will get a confirmation email regarding your order of IDT ICS9DB106BGILF PLL Clock Buffer 100 → 100 MHz 28-Pin TSSOP. You can also check on our website or by contacting our customer support team for further order details on IDT ICS9DB106BGILF PLL Clock Buffer 100 → 100 MHz 28-Pin TSSOP.
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This is PLL Clock Buffer 100 → 100 MHz 28-Pin TSSOP manufactured by IDT. The manufacturer part number is ICS9DB106BGILF. The given dimensions of the product include 6.6 x 4.5 x 1.05mm. The product is available in surface mount configuration. Additionally, it has a maximum 100mhz output frequency . It has a minimum 100mhz output frequency . Moreover, it has a maximum 150 ma supply current . In addition, the height is 1.05mm. Furthermore, the product is 4.5mm wide. Its accurate length is 6.4mm. The product has a maximum 105mhz input frequency . The package is a sort of tssop. It consists of 1 elements per chip. Whereas, the minimum operating temperature of the product is -40 °c. It has 4.6 v maximum operating supply voltage. It has a maximum operating temperature of +85 °c. It contains 28 pins.
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Don’t hesitate to ask questions for better clarification.