Nexperia HEF4011BT,653, Quad 2-Input NAND Logic Gate, 3 → 15 V, 14-Pin SOIC
Product Information
Dimensions:
8.7 x 4 x 1.45mm
Logic Family:
HEF
Width:
4mm
Input Type:
CMOS
Maximum Low Level Output Current:
4.2mA
Maximum High Level Output Current:
-4.2mA
Maximum Propagation Delay Time @ Maximum CL:
110 ns @ 50 pF
Minimum Operating Supply Voltage:
3 V
Output Type:
Buffer
Package Type:
SO
Maximum Operating Temperature:
+125 °C
Number of Inputs per Gate:
2
Length:
8.7mm
Pin Count:
14
Maximum Operating Supply Voltage:
15 V
Mounting Type:
Surface Mount
Logic Function:
NAND
Height:
1.45mm
Minimum Operating Temperature:
-40 °C
Number of Elements:
4
Propagation Delay Test Condition:
50pF
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You can order Nexperia brand products with HEF4011BT,653 directly through our website or call us at +44 (0) 3303 800 157 or email our support team at sales@enrgtech.co.uk.
Yes. Our products in Logic Gates category are shipped in lowest possible time.
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Yes. We ship HEF4011BT,653 Internationally to many countries around the world.
This is Quad 2-Input NAND Logic Gate 3 → 15 V 14-Pin SOIC manufactured by Nexperia. The manufacturer part number is HEF4011BT,653. The given dimensions of the product include 8.7 x 4 x 1.45mm. The logic family is hef. Furthermore, the product is 4mm wide. It carries cmos input type. On the other hand, it is featured with 4.2ma of max. low level output current. While a -4.2ma of maximum high level output current. It provides up to 110 ns @ 50 pf maximum propagation delay time. While its minimum operating supply voltage is 3 v. Furthermore, it has abuffer output. The package is a sort of so. It has a maximum operating temperature of +125 °c. It contains 2 inputs per gate . Its accurate length is 8.7mm. It contains 14 pins. It has 15 v maximum operating supply voltage. The product is available in surface mount configuration. The primary function of logic includes nand. In addition, the height is 1.45mm. Whereas, the minimum operating temperature of the product is -40 °c. It carries 4 elements. Features 50pf of propagation delay test condition.
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