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Reliable Clock Drivers And Distribution

New items

557G-06LF, Renesas Electronics

The Renesas Electronics 2 to 4 differential clock mux designed for use in PCI-express applications. The device selects one of the two differential HCSL input pairs and fans out to four pairs of differential HCSL or LVDS outputs. Packaged in 20-pin TSSOP Pb (lead) free packaging Operating voltage of 3.3 V Low power consumption Input differential clock of up to 200 MHz Jitter 60 ps (cycle-to-cycle) Output-to-output skew of 50 ps Available in industrial temperature range (-40 to +85°C)

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CY22150FZXI, Infineon

The Infineon Clock Generator is an extremely flexible clock generator with four basic variables that are used to determine the final output frequency. The internal PLL to generate six outputs up to 200 MHz. Able to generate custom frequencies from an external crystal or a driven source. Two wire I2C interface High accuracy outputs Low skew and low jitter Commercial and industrial operation

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AD9510BCPZ, Analog Devices

Clock Generators, Analog Devices Clock Generators/Buffers

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SI5338A-B-GM, Silicon Labs

IC CLK GEN I2C BUS PROG 24QFN

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MC100LVEP111FAG, onsemi

Clock Buffers, ON Semiconductor

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557GI-03LF, Renesas Electronics

The Renesas Electronics 557-03 is a spread spectrum clock generator that supports PCI-Express Gen 1 and Ethernet requirements. The device is used for PC or embedded systems to substantially reduce electromagnetic interference (EMI). The device provides two differential (HCSL) spread spectrum outputs. The spread type and amount are configured via select pin. Using IDT's patented Phase-Locked Loop (PLL) techniques, the device takes a 25 MHz crystal input and produces two pairs of differential outputs at 25 MHz, 100 MHz, 125 MHz or 200 MHz clock frequencies for HCSL, and 25 MHz or 100 MHz for LVDS. Supports HCSL or LVDS output levels Operating voltage of 3.3 V Input frequency of 25 MHz Jitter 60 ps (cycle-to-cycle) Spread Spectrum capability Industrial and commercial temperature ranges For PCIe Gen2 applications, see the 5V41065 For PCIe Gen3 applications, see the 5V41235

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83026BGI-01LF, Renesas Electronics

The Renesas Electronics 83026I-01 is a low skew, 1-to-2 Differential-to-LVCMOS/ LVTTL Fanout Buffer. The differential input can accept most differential signal types (LVPECL, LVDS, LVHSTL, HCSL and SSTL) and translate to two single-ended LVCMOS/LVTTL outputs. The small 8-lead SOIC footprint makes this device ideal for use in applications with limited board space. Two LVCMOS / LVTTL outputs Differential CLK, nCLK input pair CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL Maximum output frequency: 350MHz Output skew: 15ps (maximum) Part-to-part skew: 600ps (maximum) Additive phase jitter, RMS: 0.03ps (typical) Small 8 lead SOIC package saves board space 3.3V core, 3.3V, 2.5V or 1.8V output operating supply -40°C to 85°C ambient operating temperature

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8305AGILF, Renesas Electronics

The Renesas Electronics ICS8305I is a low skew, 1-to-4, Differential/LVCMOS-toLVCMOS/LVTTL Fanout Buffer. The ICS8305I has selectable clock inputs that accept either differential or single ended input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Outputs are forced LOW when the clock is disabled. A separate output enable pin controls whether the outputs are in the active or high impedance state. 4 LVCMOS/LVTTL outputs Selectable differential or LVCMOS/LVTTL clock inputs CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL LVCMOS_CLK supports the following input types: LVCMOS, LVTTL Maximum output frequency: 350MHz Output skew: 40ps (maximum) Part-to-part skew: 700ps (maximum) Additive phase jitter, RMS: 0.04ps (typical) 3.3V core, 3.3V, 2.5V or 1.8V output operating supply -40°C to 85°C ambient operating temperature Lead-Free package fully RoHS compliant

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85102AGILF, Renesas Electronics

The Renesas Electronics 85102I is a low skew, high performance 1-to-2 Differential-to-HCSL fanout buffer. The 85102I has a differential clock input. The CLK0, nCLK0 input pair can accept most standard differential input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the output during asynchronous assertion/ deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the 85102I ideal for those applications demanding well defi ned performance and repeatability. Two 0.7V differential HCSL outputs Selectable differential CLK0, nCLK0 or LVCMOS inputs CLK0, nCLK0 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL CLK1 can accept the following input levels: LVCMOS or LVTTL Maximum output frequency: 500MHz Translates any single-ended input signal to 3.3V HCSL levels with resistor bias on nCLK input Output skew: 65ps (maximum) Part-to-part skew: 600ps (maximum) Propagation delay: 3.2ns (maximum)

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85104AGILF, Renesas Electronics

The Renesas Electronics 85104I is a low skew, high performance 1-to-4 Differential/LVCMOS-to-0.7V HCSL Fanout Buffer. The 85104I has two selectable clock inputs. The CLK0, nCLK0 pair can accept most standard differential input levels. The single-ended CLK1 can accept LVCMOS or LVTTL input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Four 0.7V differential HCSL outputs Selectable differential CLK0, nCLK0 or LVCMOS inputs CLK0, nCLK0 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL CLK1 can accept the following input levels: LVCMOS or LVTTL Maximum output frequency: 500MHz Translates any single-ended input signal to 3.3V HCSL levels with resistor bias on nCLK input Output skew: 100ps (maximum) Part-to-part skew: 600ps (maximum) Propagation delay: 3.2ns (maximum) Additive phase jitter, RMS: 0.22ps (typical)

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854S006AGILF, Renesas Electronics

The Renesas Electronics 854S006 is a low skew, high performance 1-to-6, Differential-to-LVDS fanout buffer. The CLK, nCLK pair can accept most standard differential input levels. The 854S006 is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and part-to-part skew characteristics make the 854S006 ideal for those clock distribution applications demanding well defined performance and repeatability. Six differential LVDS outputs One differential clock input pair CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL Maximum output frequency: 1.7GHz Translates any single-ended input signal to LVDS levels with resistor bias on nCLK input Output Skew: 55ps (maximum) Propagation delay: 850ps (maximum) Additive phase jitter, RMS: 0.067ps (typical) Full 3.3V or 2.5V supply -40°C to 85°C ambient operating temperature

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74FCT3807DPYGI, Renesas Electronics

The Renesas Electronics clock driver built using advanced CMOS technology. This low skew clock driver offers 1:10 fan out. The large fan out from a single input reduces loading on the preceding driver and provides an efficient clock distribution network. Multiple power and grounds reduce noise. Typical applications are clock and signal distribution. TTL compatible inputs and outputs Maximum output rise and fall time < 1ns Low input capacitance 3pF typical

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